• UART IP Core Specification
  • Introduction
  • IO ports
    • WISHBONE interface signals
    • Other internal signals
    • External (off-chip) connections
  • Clocks
  • Registers
    • Interrupt Enable Register (IER)
    • Interrupt Identification Register (IIR)
    • FIFO Control Register (FCR)
    • Line Control Register (LCR)
    • Modem Control Register (MCR)
    • Line Status Register (LSR)
    • Modem Status Register (MSR)
    • Divisor Latches
    • Debug 1
    • Debug 2
  • Operation
    • Initialization
  • Architecture
  • Design Verificaiton
  • History
    • Authors & Contributors
    • Changes
      • 29.07.2002
      • 22.07.2002
      • 10.08.2001
      • 23.06.2001
      • 02.05.2001
      • 31.05.2001
      • 29.05.2001
      • 27.05.2001
    • Legacy Bugs From OpenCores
      • 1. wishbone SEL_I problem - DONE - No Issue
      • 2. Three bugs - Unknown - Under Investigation
      • 3. Typo in documentation - DONE - Added clarification
      • 4. VHDL Implementation - DONE - No Issue
      • 5. student - DONE - Fixed github issue #4
      • 6. Need to fix commenting-out style in rtl/verilog/uart_defines.v - DONE - Fixed github issue #3
      • 7. Need to fix commenting-out style in rtl/verilog/uart_defines.v - DONE - Duplicate
      • 8. about rs - DONE - No Issue
      • 9. Does uart_int.v testcase run successfully? - Unknown - Under Investigation
      • 10. TERI in Modem Status Register Not To Specification - Unknown - Under Investigation
      • 11. Problem with 16550 UART core - Unknown - Under Investigation
      • 12. Fatal bug in uart_receiver.v: srx_pad_i is not synchronized at all - DONE - Fixed May 21, 2004
      • 13. suggested receiver core fixes - @TODO - Partial, correct/needed?
      • 14. Xilinx iSim generates “out of valid range” error - DONE - No Issue